1. Field of the Invention
The present invention relates to an arrangement of a pulse generating apparatus formed on an integrated circuit.
2. Description of the Prior Art
FIG. 3 shows one example of a microcomputer having therein a so-called output comparing type 8-bit timer circuit such as disclosed in Japanese Patent Laid-Open No. 55-44700. In FIG. 3, numeral 1 represents a microcomputer, 2 designates a CPU encased therein, and 3 is a timer circuit, the CPU 2 and the timer circuit 3 being coupled through a data bus 4 to each other. Further, numeral 5 depicts an oscillation circuit having terminals XIN and XOUT between which a ceramic vibrator 6 and a bias resistor 7 are provided so as to generate a signal having a frequency inherent to the vibrator 6 in association with an amplifier 8 of the microcomputer 1, the signal being supplied to the CPU 2 and the timer circuit 3. In the timer circuit 3 there are provided four registers: a timer register 9, a comparing register 10, a timer control register comprising control registers 11a, 11b, 11c and 11d, and a timer status register 12 which are respectively coupled to the data bus 4. CPU 2 can read the data from the timer control registers 11a to 11d and further into the timer status register 12 and with the timer control register 11a to 11d. In the illustration, the coupling of the timer control register 11 and the timer status register 12 to the data bus 4 is omitted because of being not in direct relation to this invention.
Each bit of the timer register 9 and each bit of the comparing register 10 are compared with each other at each comparing section of a comparator 20 and the comparison results of all the comparing sections thereof are inputted to an 8-bit AND circuit 21 which acts as a coincidence detection circuit. The timer register 9 and comparing register 10 are respectively constructed by shift registers. Each of the comparing sections of the comparator 20 outputs an H (high level) signal only in response to the coincidence between the two inputs, and the 8-bit AND circuit 21 outputs an H signal only when all the inputs are in the high level states.
The timer circuit 3 is responsive to a clock input signal 13 and can be responsive to a signal from the oscillation circuit 5 or a signal from an external input terminal TIN, the switching operation therebetween being effected in accordance with the clock selection bit 11a of the timer register 11. Here, when the clock selection bit 11a is "1", the timer circuit 3 is coupled to the external input terminal TIN side, and when being "0", it is coupled to the oscillation circuit 5 side. Further, with the clock stopping bit 11b of the timer control register 11, the connection to the clock source can be cut through a switch. Here, when the clock stopping bit 11b is "1", the connection is established, and when being "0", the connection is cut. The timer circuit 3 outputs a comparison output signal 14 which can be coupled to an interrupt input of the CPU 2 through a switch controllable in accordance with an interrupt-allowable bit 11c of the timer control register 11. When the interrupt-allowable bit 11c is "1", the coupling is made, and when being "0", the coupling is cut.
The comparison output signal 14 is coupled to an output flag 12 making up the timer status register 12 and further to a toggle flip-flop 15. The output of the toggle flip-flop 15 is coupled through a three-state buffer 16 to an external terminal TOUT, the three-state buffer 16 is directly controllable by an output control bit 11d of the timer control register 11. Here, when the output control register 11d of the timer control register 11 is "1", the output of the toggle flip-flop 15 enters into the ON state, and when it is "0", the output enters into the OFF state, i.e., in the floating state.
Secondly, the operation will be described hereinbelow. The CPU 2 operates in synchronism with a clock supplied from the oscillation circuit 5. In the timer circuit 3, the comparison value is set in response to the CPU 2 writing data into the comparing register 10. Subsequently, an initial value of the timer is set in response to the CPU 2 writing data into the timer register 9.
When the clock selection bit 11a is set to be "0" and the clock stopping bit 11b is set to be "1", a clock input signal 13 is inputted from the oscillation circuit 5 to the timer register 9. The timer circuit 3 starts counting up the clock input signal 13, the count value always appearing at the timer register 9. The value of the timer register 9 is always compared with the value of the comparing register 10 at every bit. In response to the coincidence of all the bits, the comparison output 14 becomes "1". This output variation allows that a) the output flag 12 is set to be "1", b) the interrupt requirement is taken to the CPU 2 with the interrupt-allowable bit 11c being set to "1" and coupled to the CPU 2, and c) due to resulting in the trigger input, the output of the toggle flip-flop 15 is inverted, and in response to the output control bit 11d being set to "1", the output of the toggle flip-flop 15 is outputted through the three-state buffer 16 to the terminal TOUT.
Since the conventional timer circuit is arranged as described above, the comparison output is generated only one time at every period (count value:256) of the timer and hence the output waveform of the terminal TOUT (for example) becomes a square wave to be inverted at every period of the timer. In addition, the interrupt request occurs at every period of the timer.
Here, to change the inverting time of the output waveform with TOUT variously the comparing register 10 should be changed frequently in accordance with a program in response to every output inversion. This requires loading the data to the comparing register 10 with the program execution on the CPU 2. In addition, in the case of generating extremely shortening the interval of the output inversion, there is a further problem that it is impossible to change the comparing register 10 due to the program becomes impossible because of the long execution time of the program on the CPU 2.